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 | SUNDAY, June 6, 2004, 09:00 AM - 05:00 PM | Room: 6F | |
| WORKSHOP | ||
| UML for SoC Design | ||
| Organizer(s): Wolfgang Mueller, Paderborn Univ., Grant E. Martin, Tensilica, Inc. | ||
 UML 2.0 is nearing its final acceptance as an OMG standard and several industrial and academic groups from the EDA, embedded software and systems, and design communities around the world have started to apply it to Systems-on-Chip (SoC) designs.The DAC UML-SoC workshop is intended to coordinate those efforts, to initiate discussions, and to exchange experiences and information between those groups with a focus on UML application to SoC design and general hardware-related aspects. The program is as folllows: 9:00-9:10 am Opening Remarks by the Workshop Organizers 9:10-10:35 am UML and SoC in Japan 9:10-9:25 am - T. Hasegawa, Fujitsu Labs., Japan An Introduction to the UML for SoC Forum in Japan 9:25-10:00 am - Q. Zhu, T. Nakata, K. Kuroki, Y. Endo, T. Hasegawa, M. Mine, Fujitsu Labs., Japan Integrating UML into the SoC Design Process 10:00-10:35 am - K. Asari, H. Yoshida, M. Watanabe, CATS Co., Ltd., Japan A Difference of Model Driven Process between SoC and Software Development and a Brief Demonstration of the Tool XModelink 10:35-11:00 am Break 11:00-11:35 am Executable and Translatable UML 11:00-11:35 am - S. Mellor, J.R. Wolfe, C. McCausland, Project Technology, USA Why Systems-on-Chip Needs More UML Like a Hole in the Head 11:35-12:45 pm UML and FPGAs 11:35-12:10 pm - Th. Beierlein, Hochschule Mittweida, D. Fröhlich, B. Steinbach, Technical Univ. Bergakademie, Freiberg, Germany UML-Based Development of Applications for Run-Time Reconfigurable Architectures 12:10-12:45 pm - T. Schattkowsky, A. Rettberg, Paderborn Univ,, Germany UML for FPGA Synthesis 12:45-1:45 pm Lunch 1:45-2:55 pm UML and SystemC 1:45-2:20 pm - W.H. Tan, P.S. Thiagarajan, W.F. Wong, Y. Zhu, National Univ. of Singapore, S.K. Pilakkat, Institute for Infocomm Research, Singapore Synthesizable SystemC Code from UML Models 2:20-2:55 pm - P. Boulet, A. Cuccuru, J.-L. Dekeyser, C. Dumoulin, Ph. Marquet, M. Samyn, Université des Sciences et Technologies de Lille, R. De Simone, INRIA, G. Siegel, Esterel Technologies, Inc., Th. Saunier, Thales Communications, France MDA for SoC Design: UML To SystemC Experiment 2:55-3:25 pm Break 3:25-4:35 pm UML and SoC Methodologies 3:25-4:00 pm - M. Lajolo, NEC Labs., USA M. Prevostini, Univ. of Lugano, Switzerland UML in an Electronic System Level Design Methodology 4:00-4:35 pm - P. Green, M. Edwards, UMIST, Manchester, UK Enhancing UML to Support the Specification of Behavior for Embedded Systems-on-a-Chip 4:35-5:00 pm Conclusions, Final Remarks, and Group Discussion Please check http://www.c-lab.de/uml-soc for up to date information and organizational details. | ||